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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The philosophy of open ISAs and the RISC-V International standardization environment
- Conceptualizing RISC-V: Load-Store Architecture, Register File, and Byte Ordering
- Comparative analysis with ARM, x86, and POWER architectures: evaluating trade-offs for heterogeneous computing designs
- Evaluating ecosystem maturity through players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardized interfaces including the RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Understanding the Unprivileged Architecture specification: CSR mapping, exception handling, and memory hierarchies
- Navigating RV32I and RV64I instruction sets alongside ABI compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions essential for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Focusing on base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Implementing bitness-aware programming strategies for both 32-bit and 64-bit RISC-V targets
- Applying calling conventions and stack frame management suitable for embedded and real-time software systems
Compiler Toolchain Proficiency
- Mastering the LLVM-based compiler toolchain, including Clang, LLVM, and Binutils for RISC-V cross-compilation
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimizing code via different optimization levels, and profiling-driven tuning
- Navigating open-source toolchain development workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Utilizing Rust systems programming for RISC-V: achieving zero-cost abstractions, managing unsafe memory, and developing bare-metal software
- Navigating No-Std environments: creating custom linkers, developing device drivers, and handling memory-mapped I/O
- Developing Zephyr RTOS and Buildroot BSPs for RISC-V targets
- Interfacing peripherals: programming GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Implementing clock gating, power domain management, and low-power mode optimizations
- Analyzing cycle-accurate performance using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Working with OpenSBI (SBI specification implementation) for bootloader firmware development
- Deploying UEFI/EDK II on RISC-V to build modern firmware boot stacks
- Porting Coreboot and U-Boot for RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: working with device tree overlays, CPU topology, and AIA interrupt controller driver development
- Developing Vendor BSPs and configuring kernels for custom SoC platforms
- Implementing file system support, networking stacks, and containerization features (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Applying Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IPs such as OpenCores, the ChIPS Framework, and vendor-specific RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores (e.g., BOOM, VexRiscv, PULP) on FPGAs
- Employing SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Utilizing formal verification tools and property-based testing for RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Accelerating vector load/store operations, vector-fused multiply-add (VFMA), and matrix computations
- Optimizing workload execution with variable-length vector operations (VL, VLEN) for SIMD efficiency
- Leveraging vector mask operations, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators via custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends to support custom instruction generation and code emission
- Developing hardware-software partitioning strategies for integrating accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units: utilizing systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Applying model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
- Optimizing the memory subsystem, including HBM/DDR bandwidth management for ML model weights and activations
- Managing thermal and power budgets for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Developing Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments
- Securing the boot chain: establishing a root of trust, secure boot processes, and measured launch attestation
Cryptographic Acceleration
- Utilizing RISC-V cryptographic extensions (Zk, Zkr, K) for accelerating SHA, AES, RSA, RSA-PSS, and ECC operations
- Integrating Post-Quantum Cryptography (PQC) into next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking techniques, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastering ISA extension design methodology: encoding, encoding tables, ABI impact analysis, and the RISC-V International specification submission process
- Designing custom register files with CBAR (Custom Base Address Registers) for efficient operand dispatch
- Optimizing instruction pipelining, detecting hazards, and modifying pipelines for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using both directed and constraint-random stimulus generation
- Implementing regression testing frameworks and coverage-driven verification processes for architectural modifications
- Conducting interoperability testing to ensure custom instructions operate correctly within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors
- Establishing ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and implementing deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways with RISC-V: integrating connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Defining architecture specifications: designing ISA extensions and core configurations for a specific use case
- Implementing RTL in SystemVerilog with UVM testbenches and formal verification coverage
- Executing FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Customizing Linux BSPs and toolchains for the custom RISC-V core
- Deploying AI workloads: integrating NPUs, performing model quantization, and conducting performance benchmarking
- Validating security: enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration
- Delivering technical architecture documentation, IP strategy analysis, and cross-functional team presentations
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
